1. Field of the Invention
The present invention relates to semiconductor constructions and semiconductor device fabrication methods. More particularly, to a method of fabricating a semiconductor device which may include a material conversion (e.g., wafer backside material conversion).
2. Description of the Related Art
As semiconductor wafers are grown larger and larger, their thicknesses must be proportionally increased in order to provide sufficient physical strength during wafer handling and processing. On the other hand, increasing circuit density means more devices will be packed within a unit area, which demands an increased capability of heat removal from the chip.
In general, heat is dissipated from the front side of the chip via metal interconnects, module balls to cards and boards, etc. In addition, a large amount of the heat must be dissipated from the backside of the chip through a heat sink with or without forced air flow.
Thicker semiconductor wafers (e.g., silicon-on-insulator (SOI) wafers, silicon substrates, etc.) present a challenge on how to effectively remove the heat from the backside of the wafer (e.g., chip). The bottle neck of heat removal is now confined inside the silicon substrate. The situation becomes aggravated when a SOI substrate is used since the thermal resistance of the buried oxide is higher than that of the silicon.
Therefore, it has been recommended to use a thinner buried oxide to minimize the thermal conductivity problem. It has also been suggested to coat the backside of the wafer with a high-thermal conductive material (e.g., deposit a metal on the silicon on the backside of an SOI wafer).
It has also been recommended to thin down the chip by polishing the backside of the chip. The thinning process is carried out when the chip has been fully fabricated, tested sorted, ball attached and cut from the wafer. Each of these individual “good” chips is mounted on a holder and the back side of each chip is subjected to a hostile chemical mechanical polishing.
Clearly, there are many drawbacks to this method of “thinning down” the chip including 1) high cost—one chip will take a few hours to thin down; 2) high risk—a chip can be damaged during polishing; 3) poor control—the final thickness of the die is determined by trial and error. Precision thickness control and in-situ end point detection are difficult and expensive; and 4) poor mechanical strength—thin dies are fragile and prone to be damaged during handling.